1. Field of the Invention
The present invention relates to an optical interferometer that is formed on one PLC chip and includes an optical splitter and a plurality of Mach-Zehnder interferometers.
In particular, the invention relates to a PLC-type delay demodulation circuit including a planar lightwave circuit that modulates a DQPSK-modulated optical signal.
2. Description of the Related Art
In a 40 Gbps DQPSK communication system, as a method of configuring a delay circuit that demodulates a DQPSK (Differential Quadrature Phase Shift Keying)-modulated signal (optical signal) in a PLC, a method has been proposed which configures the delay circuit including an optical splitter and two Mach-Zehnder interferometers (MZIs) (for example, see Hashimoto, Toshikazu, et al., “Compact DQPSK Demodulator with Interwoven Double Mach-Zehnder Interferometer using Planar Lightwave Circuit”, ECOC 2008 Proceeding, Mo.3.C.2). In the device, it is necessary to reduce the size of a module, power consumption, and polarization dependence and obtain uniform MZI characteristics.
Bits of the optical signals that have been modulated by the delay circuit and then output from four output ends need to be input to four light receiving elements substantially at the same time. Therefore, the lengths of the optical paths from the optical splitter to the four output ends need to be exactly equal to each other.
In addition, as a method of reducing the size of a DQPSK receiver, a method has been examined which directly couples light output from a delay circuit configured as a planar lightwave circuit (PLC) to two balanced receivers or couples the light very close to the PLC chip using, for example, a lens. However, in this case, there are restrictions in the arrangement of the output ends of the delay circuit due to restrictions in the size or arrangement of the balanced receiver or an optical component, such as a lens, which makes it difficult to reduce the size of the delay circuit.
In order to meet the requirements and solve the problems, the following solving means have been proposed.
In the technique disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2007-232944, a half-wave plate is inserted in the central portions of the delay lines of a single MZI, and two arm waveguides of the MZI are arranged close to each other in the insertion portion of the half-wave plate. In this way, low polarization dependence is improved.
JP-A No. 2009-244483 discloses a technique capable of reducing the size of a DQPSK delay circuit including a Y-branch waveguide and two MZIs.
However, JP-A No. 2007-232944 does not disclose an arrangement structure when a plurality of MZIs is integrated.
In the technique disclosed in JP-A No. 2007-232944, when the delay circuit is designed to have a small size under various restrictions, in some cases, the flexibility of the design is insufficient. In particular, when light output from the delay circuit configured as a PLC is directly coupled to light receiving elements (PD) or when light is coupled to the PDs substantially at the same gap as that between the output ends of the PLC chip using, for example, a lens, it is necessary to increase the gap between the output ends of the first MZI and the output ends of the second MZI due to restrictions in the size of a component, such as the PD. In the structure according to the related art, in order to meet the requirements, a waveguide for adjusting the gap between the output ends is needed, which results in an increase in the size of the device.